1. Field of the Invention
The present invention relates to an external expansion bus interface circuit for connecting a micro control unit under an external expansion memory mode thereof and, more particularly, to a digital recording and reproducing apparatus incorporating said interface circuit
2. Description of the Prior Art
In FIG. 7, before describing a conventional digital recording/reproducing apparatus, a map of the tape recording format used in a digital Video Cassette Recorder (VCR) to record digital video data is shown. NTSC-format (525/60 system) Digital Video (DV)-type VCRs record 10 tracks per frame with each track comprising separate blocks to which the audio data, video data, and additional subcode data are recorded. These data tracks can be recorded to and reproduced from a tape TA by a digital recording and reproducing apparatus using a helical-scan recording/reproducing rotary head. Symbols Sc, Si, Sa, Dt, and Dh in FIG. 7 indicate a subcode, video data, audio data, tape feeding direction, and head scanning direction, respectively.
In a conventional digital recording/reproducing apparatus the digital signal processing circuit is controlled by a micro control unit using serial communications over an I2C bus. Transmitting subcode data and other additional data between the micro control unit and signal processor is programmatically controlled over a dedicated bus using plural input/output terminals.
Digital recording and reproducing apparatuses that reproduce a data signal recorded to tape using diagonal tracks as shown in FIG. 7 commonly use a rotary head and helical scanning technique. Digital recording and reproducing apparatuses achieving high density recording and a compact design also use automatic track finding (ATF) control to track the rotary head to the data tracks.
This ATF control technique works by recording a pilot signal to each track together with the data signals (e.g., audio, video, and subcode signals). A low azimuth loss, relatively low frequency signal is used for this pilot signal even for azimuth recording. During recording the frequency of the pilot signal is changed every other signal.
For example, in a DV format recording the tracks may be recorded in the sequence track f0, track f1, track f0, track f2, track f0, and so on where track f0 indicates the tracks to which the pilot signal is not recorded, track f1 indicates the tracks to which a pilot signal of frequency f1 is recorded, and track f2 indicates the tracks to which a pilot signal of frequency f2 is recorded. The signal leakage of the pilot signals from the two tracks adjacent to the main scanning track is then detected during reproduction, and the signal levels are compared to detect the level difference between the two pilot signals and thereby detect the tracking error.
The structure and operation of this conventional digital recording and reproducing apparatus is described below with reference to the accompanying figures.
In FIG. 8, a first example of the conventional digital recording and reproducing apparatus is shown. This recording and reproducing apparatus RRC1 mainly includes a micro control unit (MPU) 100 and a signal processor 120.
The micro control unit 100 controls the overall system by means of an input device 111 for inputting an information DI enabling the status of the overall system to be determined, a mode discriminator 112 for determining the operating mode of the overall system based on the information input from the input device 111, a serial interface 113 for serially transferring command data by means of the I2C bus 3 connecting the micro control unit 1 with the signal processor 120, and an additional data transfer means 14 for controlling the transfer of subcode data and other additional data to the signal processor 120 via a dedicated bus 4.
The signal processor 2 performs the digital signal processing needed to record and reproduce digital audio, video, and additional data. It accomplishes this by means of a digital signal processing circuit 21 that does the actual digital recording and reproducing processing for the audio, video, and additional data; a control register 22 for storing the control data used to control the operation of the digital signal processing circuit 21; an audio/video data memory 23 for storing the audio and video data during the processing operation of the digital signal processing circuit 21; an additional data memory 24 for storing the subcode data and other additional data during the processing operation of the digital signal processing circuit 21; a serial interface circuit 25 for serially communicating control data with the micro control unit 1 over the I2C bus 3; and a dedicated bus interface circuit 26 for communicating the subcode data and other additional data with the micro control unit 1 over the dedicated bus 4.
Note that the recording/reproducing unit for recording and reproducing the digital data Sv from the digital signal processing circuit 21 to the magnetic tape TA or other medium or to a display is omitted as shown in FIG. 8 for the sake of brevity.
The conventional digital recording and reproducing apparatus RRC1 comprised as shown in FIG. 8 operates as described below.
As described above, control data is transferred between the micro control unit 1 and signal processor 2 by means of a serial data transfer operation using the I2C bus 3. The control data includes mode information output from the micro control unit 1 and indicating the VCR status, e.g., whether the VCR is reproducing or recording data, or is stopped or paused, broadcast format information output from the signal processor 2 during tape reproduction, and the audio sampling frequency.
For example, when the user operates a button from a stop mode to reproduce the program content, the input device 11 inputs the playback (reproduction) button data (signal) and the current VCR mode to the mode discriminator 12. Based on the supplied information, the mode discriminator 12 changes the operating mode and outputs the selected mode information to the serial interface 13. More specifically, the mode discriminator 12 changes the operating mode from the stop mode to the play mode, and outputs to the serial interface 13 data indicating that the tape is to be reproduced (the play mode has been selected).
The serial interface 13 then serially transfers this mode information to the signal processor 2 according to the I2C protocol. The signal processor 2 thus receives the serial data transferred via the I2C bus 3 through the serial interface circuit 25, decodes the control data, and stores the decoded result to the control register 22. The digital signal processing circuit 21 reads the control data frame by frame, and thus changes circuit operation to the reproduction (playback) mode. Circuit operation is thus controlled on a per-frame basis.
When control data is transferred from the signal processor 2 to the micro control unit 1, the digital signal processing circuit 21 of the signal processor 2 stores the operating information as the frame-unit control data to the control register 22. More specifically, the micro control unit 1 starts the reproduction operation, and sends a transmit command through the serial interface 13 to obtain the broadcasting format information and audio sampling frequency information from the signal processor 2.
When the signal processor 2 receives this transfer command, the serial interface circuit 25 reads the control data stored to the control register 22 and serially transfers the information to the micro control unit 1 via the I2C bus 3 using the same I2C protocol. Using the control data received from the serial interface 13, the micro control unit 1 transfers the appropriate display data, for example, to the display apparatus.
The transfer of subcode data and other additional data between the micro control unit 1 and signal processor 2 is described next. The transfer of additional data is accomplished using the dedicated bus 4 while controlling the signal input/output timing using the plural input/output terminals of the micro control unit 1. The additional data more specifically refers to the time code known as the subcode information, the track number, index signals, and similar information.
During recording the micro control unit 1 sets the additional data based on the data input from the input device 11, and transfers this additional data to the signal processor 2 via the dedicated bus 4. Note that the dedicated bus 4 carries the read signal, write signal, eight address signals, eight data signals, and a strobe signal.
The additional data transferred over the dedicated bus 4 is input to the dedicated bus interface circuit 26 of the signal processor 2 and stored to the additional data memory 24. This additional data is read from the additional data memory 24 as needed by the digital signal processing circuit 21 and recorded with the audio and video data to the magnetic tape recording medium.
During the reproduction operation the digital signal processing circuit 21 of the signal processor 2 stores the reproduced additional data to the additional data memory 24. The micro control unit 1 sends a transfer command to obtain the additional data from the signal processor 2 as needed. This transfer command is more specifically a read signal and the address signal of the required additional data. When the signal processor 2 receives the transfer command the additional data stored in the additional data memory 24 is read out by the dedicated bus interface circuit 26 and output to the micro control unit 1. The output timing is synchronized to the strobe signal output from the micro control unit 1. The micro control unit 1 then interprets the additional data to, for example, convert the additional data to a linear counter value that is then sent to a display device, or to implement an image search function using the index signal.
In FIG. 9, a second example of conventional digital recording and reproducing apparatuses is shown. This digital recording and reproducing apparatus RRC2 includes a tape drive 202 for driving the recording tape TA, a micro control unit 306 for generating the control signal output to the tape drive mechanism 202, a drum 203 whereby the head is rotated to scan the tape TA and output the reproduction signal, and a reproduction amplifier 208 for amplifying the reproduction signal. Also shown are a tracking error detector 304, a video signal processor 309, and a track ID detection circuit 315. Note that the video signal processor 309 converts the amplified reproduction signal to a video signal Si, and outputs the video signal Si.
During reproduction the micro control unit 306 performs a control calculation based on the detected tracking error to generate the control signal that is then supplied to the drive circuit 211 of the tape drive mechanism 202. The drive circuit 211 supplies a drive current according to this control signal to the capstan motor 213, thereby making it possible to adjust the tape speed. This also enables the rotary head to accurately track the reproduction track.
The structure of the tracking error detector 304 is described next. The tracking error detector 304 comprises an analog-digital (A/D) converter 314, a digital error detection circuit 340, and a digital-analog (D/A) converter 344. The digital error detection circuit 340 generally comprises a bandpass filter for extracting the signal of frequency f1, a bandpass filter for extracting the signal of frequency f2, AM wave detection circuits, and a difference circuit 243, as well known to the personnel skilled in the art.
Note using a digital design for this difference circuit achieves significantly a higher degree of circuit integration, circuit reliability, and bandpass filter performance (Q value) than does an analog circuit design. Using a digital error detection circuit 340, however, requires the use an A/D converter 314. Conventional control micro control units also normally have an A/D converter built in. As a result, a D/A converter is needed for interfacing with the micro control unit. Note that this type of tracking error detection circuit is normally comprised in an IC chip discrete from the other circuits.
In FIG. 10, a third example of conventional digital recording and reproducing apparatus according to a third example of the prior art is shown in FIG. 10. This digital recording and reproducing apparatus RRC3 includes the magnetic tape TA, a signal processing circuit 400, a micro control unit 401, and a capstan motor 402 for producing a reference frame signal Sf.
The signal processing circuit 400 has a demodulating circuit 403, an inner error correction decoding circuit 404, an ATF error detection circuit 405, a track number detection circuit 406, a memory controller 407, a memory unit 408 with capacity sufficient to store at least m.times.2 frames of reproduction data, an outer error correction decoding circuit 409, and a high performance decoding circuit 410 for outputting the reference frame signal Sf to the timing controller 412 of the micro control unit 401.
The micro control unit 401 comprises a capstan motor controller 411, and a timing controller 412. The timing controller 412 detects the phase error between the frame phase of the reproduction signal and the reference frame signal Sf based on the reference frame signal Sf and the reproduction track to control the capstan motor controller 411.
When tape reproduction begins the reproduction data reproduced from the magnetic tape TA is input to the demodulating circuit 403 and ATF error detection circuit 405. The demodulating circuit 403 demodulates the reproduction data and outputs to the inner error correction decoding circuit 404 and track number detection circuit 406. The ATF error detection circuit 405 detects the synchronization error in the reproduction data, and sends an error signal to the capstan motor controller 411.
Based on this error signal, the capstan motor controller 411 synchronizes tape travel by track unit. After track synchronization is accomplished, the timing controller 412 detects the phase difference between the frame phase of the reproduction signal and the reference frame signal Sf based on the track number output from the track number detection circuit 406 and the reference frame signal Sf output from the decoding circuit 410. If a phase difference is detected, the capstan motor controller 411 is notified of the phase difference, thus enabling the capstan motor controller 411 to increase or decrease the speed of the magnetic tape TA to achieve a zero phase difference. The capstan motor controller 411 then re-references the error signal to re-synchronize the track and confirm whether the phase difference is zero.
Simultaneously to this operation of the capstan motor controller 411, the inner error correction decoding circuit 404 applies error correction decoding to the demodulated reproduction data and outputs to the memory controller 407. The memory controller 407 stores the reproduction data to the memory unit 408. The outer error correction decoding circuit 409 then applies track unit correction decoding to the reproduction data stored to the memory unit 408 based on the reference frame signal Sf output from the decoding circuit 410. The decoding circuit 410 then selects in track units m frames of the reproduction data stored in the memory unit 408 for which the outer correction decoding has been completed, outputs the data from the memory unit 408, applies high efficiency decoding, and outputs the decoded signal.